In present applications a large number of requirements is set up for switching power supplies. For example, a power supply needs to be capable of providing a large output power. Furthermore, it is required that a switching power supply comprises a low standby power consumption in case a load current provided to a circuit supplied by the power supply is comparatively small.
It was found that a low standby power can be achieved by using an active burst mode, which will be described in more detail in the following.
FIG. 7 shows an example of a switching power supply offering an active burst mode. The circuit of FIG. 7 is designated in its entirety with 700. The circuit 700 receives an alternating voltage at an input 710 and provides a converter DC output voltage at an output 712. A rectifying circuit 714 generates a DC voltage 716 which is buffered by a buffer capacitor 718. Further, a first winding 720 is connected in series with a drain-source-path of a MOS-field effect transistor 722 and a current sense resistor 724 between the DC voltage 716 and a reference potential GND, wherein the voltage over the current sense resistor 724 is a pulse voltage which is present at 772. Besides, a snubber 726 is connected in parallel with the first winding 720. A gate terminal of the MOS-field effect transistor 722 is controlled by an integrated circuit 730, which will be described in more detail in the following.
The first winding 720 is part of a transformer 740 that further comprises a second winding 742 and a third, auxiliary winding 744. The second winding 742 is connected, via a rectifying diode 746, to a filter network 748. The filter network 748 comprises two capacitors and an inductor in a H circuit configuration. An output voltage VOUT is available at the output port of the filter network 748.
The circuit 700 further comprises a feedback circuit 750. The feedback circuit 750 comprises an optocoupler 752. A current flowing through a light emitting diode of the optocoupler 752 is dependent on a voltage at an input port of the filter network 748. The current through the light emitting diode of the optocoupler 752 is further dependent on a voltage present at the output 712 of the circuit 700. Thus, the current through the light emitting diode of the optocoupler 752 increases with an increasing voltage at the input of the filter network 748. An npn-photo-transistor of the optocoupler 752 is connected between the ground potential GND and a feedback input FB of the integrated circuit 730.
It should be noted here that a collector terminal of the photo transistor of the optocoupler 752 is pulled to a voltage which is positive with respect to the reference potential GND over a resistor RFB within the integrated circuit 730. Thus, a feedback voltage at the feedback input terminal FB of the integrated circuit 730 decreases with an increasing photo current. In other words, if the voltage at the input port of the filter network 748 increases, the voltage at the feedback terminal FB of the integrated circuit 730 decreases and vice versa.
In the following section, details of the integrated circuit 730 will be described. However, for a full description of the operation of the circuit 700 reference should be taken for example to the datasheet titled “F3; ICE3AS02/ICE3BS02, ICE3AS02G/ICE3BS02G, Off-Line SMPS Current Mode Controller with Integrated 500V Startup Cell, Version 1.2”, dated Sep. 2, 2005, which is available from Infineon Technologies AG.
The integrated circuit 700 comprises a total of seven terminals. A soft start terminal 760 is connected over a capacitor 762 with the reference potential GND. The soft start pin combines the function of a soft start during a startup of the integrated circuit 730 and an error detection for an auto restart mode. These functions are implemented and can be adjusted by means of the external capacitor 762 connected between the soft start pin 760 (also designated with SoftS). The capacitor also provides an adjustable blanking window for high load jumps before the integrated capacitor 730 enters into the auto restart mode, which will be described below.
A feedback pin 764 (also designated with FB) receives an information about the regulation. The information received over the feedback pin 764 is provided to an internal protection unit and to an external pulse width modulation comparator to control the duty cycle of the MOS-field effect transistor 722. The signal at the feedback pin 764 further controls the active burst mode of the integrated circuit 730 in case of a light load at the output 712.
A high voltage pin 765 (also designated with HV) is connected to the rectified DC input voltage 716. The rectified DC voltage 716 is the input for a startup cell integrated in the integrated circuit 730.
A power supply pin 766 (also designated with VCC) is the positive supply of the integrated circuit 730. The voltage at the power supply pin 766 is derived from the third winding 744 of the transformer 740 over a one-way rectification circuit.
The integrated circuit 730 provides a drive signal to an external MOS-field effect transistor 722 over a gate pin 768.
Besides, the integrated circuit 730 senses the voltage developed over the current sensing resistor 724 (the series resistor inserted in series with the drain-source-path of the MOS-field effect transistor 722 and the first winding 720 of transformer 740). A voltage proportional to the current through the current sensing resistor 724 (and the first winding 720, unless some current is flowing through the snubber circuit 726) is fed into a current limiting circuit 770 via a current sense pin 772 (also designated with CS). If the voltage at the current sense pin 772 reaches an internal threshold of a current limit comparator CIO included in the current limiting circuit 770, the MOS-field effect transistor 722 is immediately switched off. Furthermore, the current information input into the integrated circuit over the current sense pin 772 is provided (in a scaled form) to a pulse width mode comparator C8 to realize a regulation.
The integrated circuit 730 consists of a number of blocks, which will be described in more detail in the following. A control unit 800 controls different states of the integrated circuit 730. Transitions between the operating modes, for example a soft start mode, an active burst mode, a current mode, and additional protection modes, are initiated depending on a voltage at the soft start pin 760 and a voltage at the feedback pin 764.
For the understanding of the present invention, the current mode, which constitutes a normal operation mode of the switching power supply 700, and the active burst mode, which constitutes an energy saving operation mode of the switching power supply 700, are particularly relevant. Therefore, these modes will be described in detail in the following.
The integrated circuit 730 provides the active burst mode for low load conditions at the output 712. During the active burst mode, which is controlled only by the voltage at the feedback pin 764, the integrated circuit 730 is active and can therefore immediately respond to fast changes at the feedback pin 764. At the same time, a comparatively low (lower than in the normal mode) power consumption of the switching power supply is ensured.
If the voltage at the feedback pin 764, which is low pass filtered by a low pass filter network 802, falls below a level of 1.32 volt, a comparator C5 provides a signal to the AND-gate G6. If the respective condition (voltage at feedback pin 764 smaller than 1.32 volt) is maintained for a certain period of time, a delay circuit (consisting of the OR-gate G2, switch S1, a 4.4 volt zener-diode, a 5 kΩ resistor, capacitor 762 and comparator C3) indicates that the active burst mode should be entered. The respective signal to enter the active burst mode is output by AND-gate G6. In other words, a time window is generated by combining the signal at the feedback pin 764 and the voltage at the soft start pin 760 with the AND-gate G6, which prevents a sudden entering of the active burst mode due to a large load jump. The time window is adjusted by the external capacitor 762. After entering active burst mode, a burst flag is set. An active burst mode control circuit 804 acts to limit the current flowing through the first winding 720 when the integrated circuit 730 is in the active burst mode. For this purpose, a current limit is set using the comparator C12 and the AND-gate G10, as will be described in more detail below.
Due to the current limit imposed in the active burst mode, conduction losses are reduced and a generation of audible noise by the switching power supply 700 is avoided. The operation of the active burst mode is further controlled by the voltage at the feedback pin 764, wherein the outputs of comparators C6a and C6b are used to decide whether to activate or deactivate the generation of current pulses in the first winding 720.
Upon entering the active burst mode, an internal bias of the integrated circuit 730 is switched off in order to reduce the current consumption of the integrated circuit 730. Under this condition, the MOS-field effect transistor 722 is not activated. After entering the active burst mode, the voltage at the feedback pin 764 rises, as a voltage at the output 712 of the filter network 748 begins to fall in the absence of current pulses in the first winding 720. Comparator C6a observes the voltage at the feedback pin 764.
If the voltage at the feedback pin 764 exceeds for example a level of 4V, the internal bias of the integrated circuit 730 is again activated. Thus, the integrated circuit 730 drives the MOS-field effect transistor 722 to generate current pulses, wherein the current flowing through the first winding 720 of the transformer 740 is limited to a comparatively small value, as determined by comparator C12. Due to the reactivation of the generation of current pulses in the first winding 720, the voltage in the filter network 740 increases again. Consequently, the voltage at the feedback pin 740 decreases.
If the voltage at the feedback pin 764 reaches for example a level of 3.4 volt, comparator C6b provides a signal to deactivate again an internal bias of the integrated circuit 730. As a consequence, a generation of current pulses in the first winding 720 is interrupted, until the voltage at the feedback pin 734 again reaches the above described threshold of e.g. 4.0V.
Consequently, the above-described sequence is repeated, deactivating the internal bias of the integrated circuit 730. The integrated circuit 730 remains in the active burst mode, until the load at the output 712 of the switching power circuit 700 is changed (increased). If a sufficiently high load connected to the output 712 of the switching power supply 700 is activated, the voltage at the feedback pin 764 increases. Such an increase is detected by the comparator C4. Thus, if C4 detects that the voltage at the feedback pin 764 exceeds a threshold value of for example 4.8 volt, the active burst mode is left. The output of comparator C12 is blocked upon a leaving the active burst mode, so that the current limitation imposed by the comparator C12 is no longer effective. So, after leaving the active burst mode, a maximum current can be provided (within the limits of the current limitation introduced by the comparator C10) to stabilize the voltage VOUT present at the output 712 of the switching power supply 700.
To summarize the above, the voltage at the feedback pin 764 is used to control the operation of an energy saving mode designated as active burst mode. When the voltage of the feedback pin 764 falls below a certain first threshold (e.g. 1.32 V) indicating a small load condition at the output 712 of the switching power supply, the active burst mode is entered, which results in a deactivation of the current pulses in the first winding 720 of the transformer 740. Only when the voltage at the feedback pin 764 exceeds a second threshold level (e.g. 4.0 volt), current pulses in the first winding are re-activated. As long as the integrated circuit 730 is in the active burst mode, a current limitation is imposed on the current pulses in the first winding 720, which is lower than a maximum current which is allowable when the active burst mode is inactive. If the integrated circuit 730 is in the active burst mode and current pulses are enabled, current pulses are generated in the first winding 720 until the voltage at the feedback pin 734 reaches another third threshold value (e.g. 3.4 volt). As soon as the feedback voltage reaches the third threshold value, the generation of current pulses in the first winding 720 is deactivated. Consequently, the voltage at the feedback pin 764 reaches the second threshold value (e.g. 4.0 volt) again, and the cycle is repeated. Thus, a hysteresis is achieved, as the generation of current pulses in the first winding is activated when the voltage at the feedback pin 764 reaches the second threshold value, and is deactivated when the voltage at the feedback pin reaches the third threshold value. Besides, the active burst mode is left when the voltage at the feedback pin 764 reaches a fourth threshold level (e.g. 4.8 volt).
It should be noted here, that the threshold levels described above will be referred to in the following as active burst mode threshold values.
In the following, the generation of a drive signal 810 for the MOS field effect transistor 722 will be described in detail. The drive signal 810 is generated in a pulse width modulation section 820. The pulse width modulation section 820 comprises an oscillator 822. The oscillator 822 generates two clock signals 824, 826 having the same frequency but different duty cycles. However, for the switching power supply 700 the rising edges of the first clock signal 824 and the second clock signal 826 coincide. The second clock signal 826 produces a short pulse to set a flip flop FF1. Provided the first clock signal 824 is active and a gate G8 does not provide an inhibiting signal, the setting of the flip flop FF1 results in a switching-on of the MOS-field effect transistor 722. On the other hand, as soon as the first clock signal 824 gets inactive or any of the inputs of gate G8 is activated, the MOS-field effect transistor 722 is switched off to interrupt the current through the first winding 720 of the transformer 740.
In other words, the MOS-field effect transistor 722 is activated upon a rising edge of the clock signals 824, 826 and is deactivate if either the first clock signal 824 gets inactive or any of the inputs of the gate G8 are activated. In the switching power supply 700 of FIG. 7 there are, apart from the deactivation of the first clock signal 824, four mechanisms that result in a deactivation of the MOS-field effect transistor 722.
All these mechanisms are based on a determination of the current flowing through the first winding 720 or the drain-source-path of the MOS-field effect transistor 720, respectively. The described current is sensed by the current sensing resistor 724, and a voltage proportional to the current flowing through the drain-source-path of the MOS-field effect transistor 722 is therefore provided at the current sense pin 772 of the integrated circuit 730. An input filtering is applied to the voltage at the current sense 772 of the integrated circuit 730 by a filter and input protection circuit 828. Further, a leading edge of the voltage at the current sense pin 772 is suppressed in a leading edge blanking circuit 830. A current describing signal 832, which is derived from the voltage at the current sense pin 772 and describes the current through the drain-source-path of the MOS-field effect transistor 722 (with the exception of leading edges, which are suppressed in the leading edge blanking circuit 830) is fed as an input signal into comparators C10 and C12. Comparator C10 compares the signal 832 with a threshold signal describing a maximum allowable current. If the current describing signal 832 exceeds the threshold signal applied to comparator C10, the comparator C10 sends an active signal to gate G8, which results in a deactivation of the MOS-field effect transistor 722. In other words, as soon as the current through the drain-source-path of the MOS-field effect transistor 722 exceeds a predetermined level, the MOS-field effect transistor 722 is switched off, so that a further increase of the current is avoided. So, comparator C10 provides a current limitation in the normal operation mode (non-energy saving operation mode).
Besides, when the integrated circuit 730 is in the active burst mode, the output of comparator C12, which compares the signal 830 to a predetermined current threshold signal (smaller than the current threshold signal provided to comparator C10), is coupled to the input of gate G8 over the AND-gate G10. In other words, in the active burst mode the MOS-field effect transistor 722 is deactivated as soon as the current describing signal 832 exceeds the value of the current reference signal applied to comparator C12.
The current describing signal 832 is further scaled to provide a scaled current describing signal 834 derived from the current flowing through the drain-source-path of the MOS-field effect transistor 722. The scaled signal 834 is compared with a low pass filtered feedback signal 840 derived from the signal present at the feedback pin 764 of the integrated circuit 730 in a pulse width modulation comparator C8. If the scaled signal crosses a threshold level defined by the (low pass filtered) feedback signal 840, the output of the pulse width modulation comparator C8, which is coupled to an input of the gate G8, is activated. Thus, in response to an activation of the output of the pulse width modulation comparator C8, the MOS-field effect transistor 722 is switched off.
Furthermore, during the startup of the integrated circuit 730, a signal provided by a soft start circuit 850 is effective to the switch of the MOS-field effect transistor 722.
In the following, in order to facilitate the understanding of the circuit 700, the (normal, current mode) operation of the circuit 700 will be described, based on the assumption that the integrated circuit 730 is neither in a soft start condition nor in an active burst mode condition, and that further the current limiting comparator C10 is inactive.
In this case, a duty cycle of the drive signal 810 for the MOS-field effect transistor 722 is determined by a regulation loop, wherein the voltage at the feedback pin 764 is derived from the voltage present in an output circuit of the switching power supply (the output circuit consisting of the second winding 742, the rectifying diode 746 and the filter network 748). The feedback signal 840 serves a reference signal for the pulse width modulation comparator C8. As soon as the scaled signal 834 descriptive of the current flowing through the MOS-field effect transistor 722 crosses a level defined by the feedback signal 840, the output of the comparator C8 is activated. In the response to the activation of the output of the pulse width modulation comparator C8, the MOS-field effect transistor 722 is deactivated after a delay time. If the voltage in the output circuit 742, 746, 748 of the switching power supply 700 is comparatively high, the feedback signal 840 has a comparatively low value. Thus, the output of the pulse width modulation comparator C8 is activated at a comparatively small value of the current flowing through the MOS-field effect transistor 722. Consequently, the duty cycle of the current flowing through the first winding 720 of the transformer 740 is comparatively low, which results in a reduction of the voltage in the output circuit of the switching power supply 700. In contrast, if the voltage in the output circuit 742, 746, 748 of the switching power supply 700 is comparatively low, the feedback signal 840 is comparatively high, which results in a comparatively high duty cycle of the current flowing through the first winding 720 of the transformer 740. This results in an increase of the voltage present in the output circuit of the switching power supply 700.
However, it was found that for example for a small load present at the output 712 of the switching power supply 700, the voltage of the feedback signal 840 (in an equilibrium state) varies significantly with changes of the DC voltage 716, which brings along significant problems when controlling activation and/or deactivation of power saving modes (like the active burst mode) on the basis of the feedback signal 840.